Field of the Invention
The present disclosure generally relates to a package structure and a manufacturing method thereof. More particularly, the present disclosure relates to a chip package structure and a manufacturing method thereof.
Description of Related Art
Semiconductor industry is one of the most developed hi-technology in recent years. With the technology advancing, the hi-tech electronics industries have developed thinner, lighter and more compact products with artificial intelligence and better functions.
In certain categories of conventional packaging technologies, such as fan-out wafer level packaging (FO-WLP), a post-passivation interconnect (PPI) structure (also known as redistribution layers (RDLs)) may be formed over the passivation layers of a die and electrically connected to the bond pads. This is followed by the formation of a dielectric layer and under bump metallurgies (UBMs). The UBMs are formed in openings penetrating through the second polymer and electrically connected to the PPI structure. I/O pads such as solder balls may then be placed on the UBMs. However, an issue with this packaging technology is reliability concerns regarding delamination of the dielectric layer. Delamination issues have been observed in typical FO-WLP wafers subject to various durability tests. These delamination issues may further cause I/O pad breakages in the integrated circuit and reduce the reliability of package and the processing yield.